1. Field of the Invention
The present invention relates to a method of disposing a dummy pattern in a wiring process of a semiconductor integrated circuit having a multilevel wiring structure, the dummy patterns being used to planarize the surface of a layer and the reduction of voltage noise among wires.
2. Background Information
In recent years, in order to increase the density and integration of a semiconductor integrated circuit, a multilevel wiring structure has been adopted. In this multilevel wiring structure, wirings are arranged in a plurality of layers in a thickness direction of the semiconductor integrated circuit. In such multilevel wiring structure, in order to prevent problems in the wirings, such as the breaking of wires, caused by concavity and convexity in each layer, the layers need to be made highly planar. The most widely used method of planarizing a surface of an interlayer insulation film formed on the wiring is a method using a CMP (chemical mechanical polishing) method. However, with respect to this CMP method, if there is any deviation in the density of a wiring arrangement that is the foundation of the interlayer insulation film, i.e. if there are dense and non-dense portions in the wiring pattern, there is a possibility that some concavity and convexity will still remain on the surface of the interlayer insulation film even after the polishing, meaning that the surface of the interlayer insulation film will not be made completely planar. In order to resolve this problem, a dummy pattern, i.e. an electrically floating metal piece, is arranged in the non-dense portion of the wiring, and therefore the density of the wiring is made uniform.
For example, Japanese Laid Open Patent Application No. H10-335326 (hereinafter to be referred to as Patent Reference 1), Japanese Patent Application Laid Open No. H10-178013 (hereinafter to be referred to as Patent Reference 2), Japanese Laid Open Patent Application No. 2000-277615 (hereinafter to be referred to as Patent Reference 3) and Japanese Laid Open Patent Application No. 2001-20327 (hereinafter to be referred to as Patent Reference 4) disclose inventions relating to a dummy pattern disposal.
According to the invention disclosed in Patent Reference 1, a linear dummy pattern is placed between two adjacent wirings and in parallel with the wirings.
According to the invention disclosed in Patent Reference 2, a dummy pattern separated from the wirings by a predetermined distance is disposed so that a pattern density is made uniform by a pattern forming method including: a) a process of enlarging a wiring pattern by a predetermined measurement in terms of two dimension; b) a process of generating a reversal pattern by reversing the enlarged wiring pattern; c) a process of superimposing a superimposing pattern and the reversal pattern and leaving only the region which is redundant between the two patterns as a dummy metal pattern, the superimposing pattern having a plurality of same geometrical forms being arranged systematically at predetermined intervals.
According to the invention disclosed in Patent Reference 3, a region where the wirings are formed is divided into a number of blocks, among which base dummy metal patterns with low metal density are formed in the blocks in the vicinity of the metal wiring and base dummy metal patterns with high metal density are formed in the blocks which are apart from the metal wiring.
According to the invention disclosed in Patent Reference 4, a dummy pattern for adjusting the area ratio of a chip layout is formed on each layer while one dummy pattern has the same shape as of the dummy patterns in other layers and overlaps the other dummy patterns formed in other layers. Furthermore, by having the dummy pattern in each layer connected to either the power supply wiring (hereinafter to be referred to as a VDD wiring) or the ground wiring (hereinafter to be referred to as a GND wiring), a power source capacitance for decreasing radiant noise caused by an instantaneous current of the semiconductor integrated circuit is configured.
In order to make the wiring density uniform, it is desirable that the dummy patterns are disposed as evenly as possible in the free spaces among the wires. However, disposing the dummy patterns without any restriction might result in causing unnecessary capacitive connections among different wirings, which can induce problems such as changing the circuit characteristics, increasing the parasitic capacitance to cause signal delay, etc. Therefore, in disposing the dummy patterns, it is necessary to give consideration to the influences of possible changes in the parasitic capacitance and voltage noise which are accompanied by the dummy pattern disposal, in addition to making the pattern density uniform.
In accordance with the inventions of Patent References 1 to 3, a possible increase in the parasitic capacitance accompanied by the dummy pattern disposal is controlled by adjusting the disposing intervals or the pattern, etc. of the dummy patterns, but no direct consideration is given to the influences of possible voltage noise generated among wires in disposing the dummy pattern. Accordingly, with respect to these prior art inventions, there is a possibility that those wires which are normally not affected by the voltage noise might be affected by the voltage noise due to disposing the dummy patterns.
According to the invention disclosed in Patent Reference 4, the power source capacitance is configured in order to decrease the radiant noise caused by the instantaneous current of the semiconductor integrated circuit. The invention does not give consideration to disposing the dummy patterns considering the influences of possible voltage noise generated among wires in disposing the dummy pattern.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of disposing dummy pattern in a semiconductor integrated circuit. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.